Conventionally, a power supply noise occurs when a power supply current that flows at switching of a CMOS logic circuit passes through an inductor of a bonding wire of a package. Such power supply noise frequently occurs in digital circuits, and it adversely affects other equipment by electromagnetic interference (EMI). Further, in an analog/digital (A/D) mixed LSI, a noise that occurs in a digital circuit is transmitted through a substrate to an analog circuit, and adversely affects the performance of the analog circuit. This is known as “substrate noise”.
The mechanism of occurrence of such power supply noise will be described with reference to FIG. 16.
In FIG. 16, a power supply terminal 121 and a ground terminal 122 of an LSI chip 120 are connected to an external power supply 150 of a package 130 through bonding wires having inductance components (inductors 140A and 140B), respectively. Further, in the LSI chip 120, an inverter circuit 131 of a CMOS structure, internal load 90 (90cp and 90cn), and a bypass condenser (decoupling capacitor) 111 are arranged in parallel. When an input voltage to the internal circuit of the TST chip 120 changes from a “L” level to a “H” level, a discharge current flows. At this time, a current path is formed through a node 132 at an output end of the inverter circuit 131 as shown by the arrow in FIG. 16.
In this case, the direction of the current passing through the inductor 140A connected to the power supply terminal 121 and the direction of the current passing through the inductor 140B connected to the ground terminal 121 are opposite to each other viewed from the inside of the LSI chip 120 due to fluctuations in the input voltage, whereby noises of opposite phases occur at the power supply terminal 121 and the ground terminal 122, respectively. Assuming that the power supply voltage is Vdd, the ground voltage is Vss, and the maximum voltage fluctuation width due to noise is Vn, an initial voltage fluctuation of Vdd−Vn occurs at the power supply terminal Vdd while an initial voltage fluctuation of Vss+Vn occurs at the ground terminal 122, and subsequently, a ringing operation due to an RLC circuit occurs, whereby symmetrical noises having opposite phases occur at the power supply terminal 121 and the ground terminal 122, respectively.
A typical method for reducing such power supply noise is to provide a bypass condenser 111 between the power supply terminal 121 and the ground terminal 122. In FIG. 16, the bypass condenser 111 is provided in the LSI chip 120. Since the internal load 90 is operated using electric charge stored in the bypass condenser 111, fluctuations in the amount of current supplied from the external power supply 150 through the inductors 140A and 140B can be suppressed, resulting in a reduction in noise.
Further, as the bypass condenser 111 is placed closer to the noise source (e.g., bonding wire), the noise reduction effect is enhanced. Ideally, the bypass condenser 111 should be placed in the same position as the operating circuit to minimize the amount of noise.
As a conventional method for providing such bypass condenser 111 on an LSI chip 120, Japanese Published Patent Application No. 2000-208634 discloses a method for fabricating a bypass condenser in a vacant area after layout design.
However, there may arise a case where a bypass condenser having a required capacitance cannot be secured by only the vacant area after layout design.
On the other hand, as a method for mounting a bypass condenser having a required capacitance, there is disclosed a method for optimizing the capacitance of a bypass condenser by repeating circuit simulation and floor planing, in “Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design”, 1997 Design Automation Conference, Haward H. Chan et al.
In this method, first of all, an initial layout of functional blocks is input to a floor planner. Next, an area n where noise occurs frequently is specified by circuit simulation, and a capacitance Cn of a bypass condenser, which is necessary for reducing the amount of noise to a predetermined value or lower in the specified area n, is calculated.
Next, the total of bypass condensers to be added is modeled as at least one virtual block bk having a capacitance larger than the capacitance Cn, and the virtual block bk is inserted between the already-arranged functional blocks.
In the conventional structure, however, even if a bypass condenser having a required capacitance is placed in a vacant area after layout design, the position where the bypass condenser is placed is between a circuit block and a circuit block, and therefore, the bypass condenser is distant from the noise source in the circuit block, resulting in little effect of noise reduction.